Flash-based storage devices are popularly used for long-term data logging since they have the following properties: cost-effectiveness, high capacity and low power. FIG. 1 shows the way the storage elements of a typical sensing platform are connected to the microcontroller unit (MCU) and sensor devices. Although serial flash and secure digital (SD) cards are capable of high I/O bandwidth, in practice, most data loggers for low-power sensing systems never achieve anywhere near the rated bandwidth and spend far more energy to write data in it. The bottleneck is not due to a single factor but a combination of the I/O architecture and scheduling. At the same time, the low-power requirement precludes the use of high-performance, parallel busses, and the high cost of making a custom integrated circuit (IC) limits the choice of MCUs to those commonly chosen for sensor nodes today. Therefore, any solution to overcoming the data logging performance of sensing platforms considered here must use the same existing serial peripheral interface (SPI) bus.
Although the SPI may be a bottleneck, it is not the only issue, as flash memory itself imposes wait cycles on page or block levels such that the MCU can be stalled for a long time if not scheduled carefully. For example, the multiple-sector write mode shows far better write performance than the single-sector write mode in an SD card as shown in the FIG. 2. To enable the multiple-sector write mode, it is required to allocate a large amount of internal SRAM included in the MCU; however, the low-power microprocessors cannot afford to allocate that large amount of internal SRAM as a buffer for the SD card. One may consider alternative nonvolatile memory technologies such as FRAM, or MRAM, which consume low power, do not impose long wait cycles, and are byte-addressable as a replacement of the Flash-based storage devices. However, FRAM is much more expensive than flash, which has limited the use of FRAM to mainly storing configuration and short-term data as a replacement of EEPROM.
Hybrid-Storage
There have been efforts to adopt hybrid storage systems to make the best result out of the combination of different types of memory, although existing storage capabilities on sensor nodes are restricted to a single flash memory in most cases. Internal EEPROM included in the MCU is often used to store metadata for the file systems and snapshots. Since EEPROM allows writing a byte at a time, in-place updates and more reprogramming capability, it is more suitable for handling metadata that tends to be updated more often with a small amount of changes. However, the amount of EEPROM is very limited while the time to complete an operation to write a byte is very long (8.5 ms for a byte), which slows the overall write speed.
NVFAT, FRASH, and Chameleon suggest the use of more advanced non-volatile memory called FRAM. FRAM is byte-addressable for write operation and much faster than NAND flash or EEPROM; therefore, it is a good candidate to replace EEPROM for storing metadata. NVFAT modifies the VFAT file system in Linux to use non-volatile memory such as FRAM as a cache for metadata of the file system. FRASH is a file system dedicated to a flash memory. It differentiates itself from other flash file systems by using FRAM as metadata storage. Chameleon is a solid-state drive that adds FRAM to flash memory. Chameleon has an FTL to provide transparent access to flash memory by maintaining a mapping table keeping pairs of the logical address and physical address and some other metadata. Chameleon uses FRAM to store the metadata including the mapping table to boost the performance, since FRAM is good for small data update, whereas NVFAT and FRASH use FRAM as metadata storage for a particular file system. However, all of these require a large amount of expensive FRAM space and use FRAM as a part of the memory architecture rather than the storage. Therefore, these systems are not feasible to currently available sensor platforms.
Although the FRAM chips used for the above systems have parallel interfaces, FRAM chips are also available with serial interfaces such as SPI or I2C, which can be easily employed for sensor systems. Several sensor systems have adopted serial FRAM as a part of the hybrid storage system. MStore, an expansion board for sensor platforms such as Telos and Mica nodes, brings up multiple types of non-volatile memory chips. MStore provides SPI NOR flash, NAND flash, and SPI FRAM, all connected to the same SPI bus. The goal of MStore is to allow researchers to easily experiment with using the various types of memory chips. These three memory chips have different properties and can make good combinations for certain flash file systems for sensor platforms. However, MStore board requires large amounts of resources to be used for legacy file systems, and a direct transaction from a storage device to the other is not possible on SPI master-slave I/O architecture.
DuraMote employs a storage system consisting of an SD card and FRAM. DuraMote support FAT32 file system for logging data so that a PC can read data. The limited internal SRAM size of the MSP430 MCU included in the sensor system is shared by multiple tasks, and single-sector write mode is used to transfer data to the SD card. FRAM is solely used for configuration information and some critical data. Since the SD card and the FRAM are connected to the same SPI bus of the MCU, using FRAM as external buffer forces double transactions just like MStore.
Enhanced Master-Slave Bus Architecture
The master-slave bus architecture does present a flaw, namely the double transaction problem. The name comes from the fact that two transactions are needed to send data between two slave devices, because the protocol requires that the master be involved in every transaction and that one slave cannot directly communicate with other slaves. As a result, the maximum transfer rate between two slave devices is half of what the channel is physically capable of. Also, since the host MCU acts as a middleman in a transfer, it has to use resources to setup the transfer, buffer the data from the source slave, and funnel it back out to the sink slave. The technique of pipelining transactions through the use of multiple channels dedicated to the slave devices could parallelize the transfer, but it still takes up buffering space and does not save power.
Master-Handoff Protocol (MHP) addresses the double transaction problem with specialized protocol. In this protocol, the MCU becomes a slave and either the source or the sink device becomes a temporary master after the MCU issues a read command to the source slave device and a write command to the sink slave device. MHP can get rid of the double transaction involving multiple SPI slaves whose protocols can be programmed accordingly.
Paused-Switch Circuit (PSC) takes a hardware approach to addressing the double-transaction problem by providing a more flexible SPI controller to the MCU rather than introducing a new protocol. Unlike MHP, PSC can be applied to any currently available SPI devices without modifying their protocols.
To allow for two slave devices to transfer data, the master sets up the source and sink slave devices separately by issuing the respective read or write command code but pauses them before “splicing” their bulk data transfer phase. Neither the source slave nor the slave is aware of the fact that their data lines have been rewired to enable direct slave-to-slave transfer, because the master pauses the clock to one slave and leaves the chip-select asserted (or else the transaction will be aborted) while switching to setting up the other slave. Once the source and slaves are aligned in their transactions and the data-in/data-out lines are re-wired, slave-to-slave transfer can occur. This approach enables a master to use one single SPI controller to nearly fully utilize the SPI bus and eliminate the double-transaction problem. This approach can be accomplished with simple hardware support.
PSC proposes transaction splicing and source broadcast mode to handle the required steps. Transaction splicing allows the master device to be able to keep each chip-select pin asserted to prevent the transaction state from being reset while issuing a command to another slave, and to isolate each SCK line so that the master device can issue a command to a slave device individually even though the chip-select pins of all the slaves are asserted. Source broadcast mode allows a slave device to broadcast its data through its SPI output pin to all the input pins of other slave devices and the master by temporarily inverting the source-slave's slave-out (SO) signal to drive the MOSI bus signal. Since all the slaves' slave-in (Si) pins are connected to the MOSI pin of the master device, the source-slave SO signal is broadcast to all of the other devices including the master device.
Limitations of Currently Used Storage Compositions
First, sensor storage systems' logging performance is far behind the rated storage bandwidth provided by SD cards. Since the embedded MCU's cannot afford allocating enough memory out of the internal SRAM to enable multiple-page-write required to match the rated bandwidth, high sampling rates cannot be supported. Even if enough memory as write buffer to the SD card can be allocated, buffering in non-volatile memory may result in possible data loss by power failure.
Second, external fast non-volatile memory such as FRAM chips as write buffer can be added to offer enough space for buffering data instead of using them as metadata storage only. However, the double transaction problem took place when the buffered data in the FRAM chips is flushed to the SD card. To flush buffered data from FRAM chips to the SD card, two identical data transactions have to be performed due to the master-slave bus architecture. These double transactions incur more CPU time and memory for transactions as well as more time on transfer time.
Third, the ideas such as MHP and PSC to address the double transaction problems can be used but each of them imposes problems. While MHP works for MCU-based slaves, it is not possible for many slave peripherals whose protocols are hardwired. In addition, a clock generator has to be equipped in each slave device, which increases not only the hardware complexity but also the power consumption. PSC is not able to handle multiple numbers of transactions simultaneously on the same bus, which eventually blocks data transmission from MCU to any slave device on the master-slave bus while a slave-to-slave transaction is being performed. Additionally, the CPLD that is used for implementation consumes too much power and it is not realistic to waste that much power only for the controller to get rid of the double transaction problems.
Fourth, energy consumption for sensor systems is always one of the most important issues. In fact, sensing systems are deployed in remote places where no constant power source is available and wireless transmission is limited, for example, water pipes in manholes. Even though alternative power sources like solar panels can be used, it is always a requirement that energy consumption be minimized to guarantee reliable data aggregation. The single-page-write mode has been found to not only lowers the storage bandwidth, but also incur a lot higher energy consumption.
Therefore, it is desirable to provide serial bus with improved performance and efficiency.